1. Field of the Invention
The present invention relates to a data output buffer, in semiconductor memory device, for transmitting data read out from memory cells to an external logic circuit, and more particularly to a data output buffer that can improve the reading speed of a semiconductor memory device by improving the transition speed of output data.
2. Description of the Prior Art
A general data output buffer included in the semiconductor memory device converts true and complementary data signals from memory cells to a three-logic output data signal. The conventional data output buffer supplies the converted data signal to an external logic circuit via an output terminal. The output data signal generated by the conventional data output buffer has high logic of a predetermined voltage level when the true data signal has a specific logic, and has low logic of grounded potential GND when the complementary data signal has a specific logic. The output data signal of the data output buffer has a reference logic of high impedance when both the true and complementary data signals have ground logic.
However, the conventional data output buffer cannot maintain high impedance, due to the input impedance of external logic circuit connected to the output terminal, the impedance of transmission line connected between the output terminal and the external logic circuit, etc. The reference logic of high logic has a voltage level which is gradually increased from low logic of grounded potential or a voltage level which is gradually decreased from high logic of specific voltage, due to the impedance of transmission line and the input impedance of external logic circuit. Because of this, the conventional data output buffer creates a large transition voltage width and a long transition interval of the output data, and thereby decreases the data reading speed of semiconductor memory device. The problem of the above conventional data output buffer is described with reference to the attached drawings.
FIG. 1 illustrates a conventional data output buffer which has a first invertor 10 for inverting a true data signal from a first input line 11, a second invertor 12 for inverting an output enable signal from a control line 15, and a NAND gate 14 for receiving the inverted true data signal and the inverted output enable signal from the first and second inverters 10 and 12. The NAND gate 14 NAND-gates the inverted true data and the inverted output enable signal and supplies the NAND-gated signal to a pull-up PMOS transistor 18. As shown in FIG. 2A, the NAND-gated logic signal has low logic when both the inverted true data signal and the inverted output enable signal have high logic. The pull-up PMOS transistor 18 opens and closes a current path of first power supply voltage Vcc that will be supplied from the first power supply Vcc to the output line 17 according to the logic value of the logic signal from the NAND gate 14.
The conventional data output buffer additionally comprises a NOR gate 16 for receiving the complementary data signal from the second input line 13 and the output enable signal from the control line 15, and a pull-down NMOS transistor 20 connected between the output line 17 and the second power supply GND. The NOR gate 16 NOR-gates the complementary data signal and the output enable signal and supplies the NOR-gated logic signal to the gate of pull-down NMOS transistor 20. As shown in FIG. 2B, the logic signal generated in the NOR gate 16 has high logic when both the complementary data signal and the output enable signal have low logic. The pull-down NMOS transistor 20 opens and closes a current path of the second power supply voltage GND that will be supplied from the second power supply GND to the output line 17, according to the logic value of the logic signal from the NOR gate 16.
The output data signal generated in output line 17 maintains the first power supply voltage Vcc supplied via the pull-up PMOS transistor 18 while the pull-up PMOS transistor 18 is turned on. On the other hand, while the pull-down NMOS transistor 20 is turned on, the output line 17 has the second power supply voltage GND supplied via the pull-down NMOS transistor 20. While both the MOS transistors 18 and 20 are turned off, the output data signal generated in the output line 17 has voltage gradually decreased from the first power supply voltage Vcc or voltage gradually increased from the second power supply voltage GND, as shown in FIG. 2C. The reason why the output data signal has the voltage gradually increased from the first power supply voltage Vcc and the voltage gradually increased from the second power supply voltage during the turning-off of both MOS transistor 18 and 20 is due to the capacitance and resistance input impedance of the external logic circuit connected to output line 17.
FIG. 3 shows a conventional data output buffer which has a pull-up NMOS transistor 24 instead of the pull-up PMOS transistor 18 as shown in FIG. 1, and a NOR gate 22 instead of the NAND gate 14 and two inverters 10 and 12 as shown in FIG. 1. The NOR gate 22 generates a "high" logic signal, as shown in FIG. 4A, when both the true data from the first input line 11 and the output enable signal from the control line 15 have low logic. The pull-up NMOS transistor 24 supplies the first power supply voltage Vcc from the first power supply Vcc to the output line 17 while the logic signal from the NOR gate 22 maintains high logic.
The NOR gate 16 generates a "high" logic signal, as shown in FIG. 4B, when both the complementary data from the second input line 13 and the output enable signal from the control line 15 have low logic. Then, the pull-down NMOS transistor 20 supplies the second power supply voltage GND from the second power supply GND from the output line 17, in response to a "high" logic signal from the NOR gate 16.
The output data signal generated in the output line 17 maintains the first power supply voltage Vcc supplied via the pull-up NMOS transistor 24 while the pull-up NMOS transistor 24 is turned on. On the other hand, while the pull-down NMOS transistor 20 is turned on, the output line 17 has the second power supply voltage GND supplied via the pull-down NMOS transistor 20. While both the MOS transistors 20 and 24 are turned off, the output data signal generated in the output line 17 has the voltage gradually reduced from the first power supply voltage Vcc or the voltage gradually increased from the second power supply voltage GND, as shown in FIG. 4C. The reason why the output data signal has the voltage gradually reduced from the first power supply voltage Vcc and the voltage gradually increased from the second power supply voltage GND during the turning-off of both transistors 20 and 24 is due to the capacitance and resistance input impedance of the external logic circuit connected to the output line 17.
As described above, the conventional data output buffer cannot maintain the high impedance state, i.e., the reference logic level, due to the input impedance of the external logic circuit connected to the output line, and generates the output data signal having the reference logic of the voltage level being nearly equal to the voltage level of high logic or the voltage level of low logic. This increases the voltage difference between the reference logic and the high logic and the voltage difference between the reference logic and the low logic, and reduces the transition speed of output data signal of the data output buffer. The decrement in the transition speed of the output data signal of the data output buffer deteriorates the data reading speed of the semiconductor memory device.